1. Field of the Invention
This invention relates to methods of fabricating a packaging structure, and more particularly, to a method of fabricating a packaging structure that may increase yield and reduce cost.
2. Description of Related Art
In order to meet the packaging requirements of high integration and miniaturization for semiconductor packages, and to provide a packaging substrate that allows a plurality of active and passive element to be installed thereon, a multiple-layered board is replacing a single-layered board gradually. Therefore, a layout area may be increased through the use of an interlayer connection technique, and the requirement of highly integrated circuit may be formed on the multiple-layered board.
A multiple-layered circuit board of the prior art comprises a core board and two built-up structures symmetrically installed on two surfaces of the core board. The use of the core board causes the circuit board to have a long conductive wire and thicker structure, which is contradictory to the requirements of increasing performance and reducing sizes. A circuit board that has a coreless structure comes to the market, in order to satisfy the demands of shorten conductive length and reduced structure thickness.
In the modern flip chip semiconductor packaging technique, a semiconductor chip having an active surface is installed on a packaging substrate having a plurality of conductive lands on a top surface thereof, and a plurality of electrode pads are installed on the active surface and are electrically connected via solder bumps to the conductivelands, allowing the semiconductor chip to be electrically connected to the packaging substrate.
Compared with a conventional wire bond technique, the flip chip technique is characterized in that the electrical connection between the semiconductor chip and the packaging substrate is realized by the solder bumps, rather than by a common gold wire. The flip chip technique has advantages of high packaging density and small packaging size. Without using the longer gold wire, the flip chip technique may reduce the resistance and improve the electric functionalities.
A method of fabricating a packaging structure according to the prior art provides a panel of substrate body that has a front-end fabricating process completed and includes a multiple-layered circuit connection structure, an outermost circuit of the panel of substrate body having a plurality of bump pads; forms on the substrate body an insulating protection layer having a plurality of openings formed therein, allowing the bump pads to be exposed from the openings; forms a surface treatment layer on the bump pads in the openings, so as to form a panel of packaging substrate (panel); cuts the panel of packaging substrate into a plurality of packaging substrate units or a plurality of packaging substrate strips, each of the packaging substrate strips having a plurality of packaging substrate units; and, transfers the packaging substrate strips to a packaging factory for subsequent chip attachment, packaging and/or singulation processes.
However, if the chip attachment and packaging processes are performed after the panel of packaging substrate is cut into the packaging substrate units, only one of the packaging substrate units is processed at one time, which reduces the yield and increases the cost. Moreover, if the chip attachment, packaging and singulation processes are performed after the panel of packaging substrate is cut into the packaging substrate strips, each of the packaging substrate strips has to have a rim reserved for the packaging substrate strip to be clamped during the subsequent processes. The rim occupies too much the area and wastes the material cost.
With the packaging substrate becoming thinner and thinner, it is more and more difficult to perform the chip attachment or packaging process on the packaging substrate units or packaging substrate strips.
If the chip attachment, packaging and singulation processed are performed on the panel of substrate, without cutting the panel of packaging substrate into a plurality of packaging substrate units or a plurality of packaging substrate strips in advance, a larger semiconductor equipment is required. Accordingly, the equipment cost is increased. Besides, the larger the area of the panel of packaging substrate is, the lower the precision becomes. Therefore, the final packaging structure units have a larger fabricating error, which affects the yield.
Therefore, how to solve the problems of the method of fabricating a packaging structure of the prior art that the fabricating steps are complicated, yield is low, too many effective area of the substrate is wasted and the cost is high is becoming one of the most popular issues in the art.